Nanofabrication Competition - CLOSED
CMC Microsystems is evaluating a new fabrication process developed in collaboration with Applied Nanotools (ANT) and Institut National d'Optique (INO).
About the Technology:
- The NanoSOI process is conducted on a thin SOI wafer.
- The silicon and the deposited metal are patterned using e-beam lithography.
- The buried oxide is isotropically etched to release the nano structures.
This process has under gone preliminary testing and is ready for further exploration by researchers involved in nanotechnology applications requiring the nano patterning of metal and silicon. Three different example applications of the NanoSOI process are:
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Photonics Crystal Ban |
Nanobeam Resonator |
THz Phase Retarder |
Process Options:
- Silicon-On-Insulator: Two thickness options are available: 145 nm and 300 nm.
- Metal: Two options are available: Aluminum and Chromium/Gold.
- Process Flows: Based on the end goal of the process, 6 different flows are available. Please refer to the design manual for a description of the available options for the NanoSOI process.
Application Deadline: January 10, 2010
For more information about the NanoSOI process, design size requirements, pricing, and related topics, please contact:
Dr. Imed Zine-El-Abidine, Senior Engineer, Micro/nanotechnology Fabrication, CMC Microsystems 613.530.4795, imed@cmc.ca |
